1. Field of the Invention
The present invention relates to semiconductor devices such as a memory, a processor and the like, and an information processing system which comprises these semiconductor devices.
2. Description of the Related Art
Japanese Patent Application Laid-open No. 06-214881A (hereinafter called Patent Document 1), for example, describes a memory control method for reducing power consumption by shifting a refresh timing from one memory bank to another, in a memory which includes a plurality of memory banks. Patent Document 1 describes that the refresh timing is shifted from one memory bank to another in units of clock signal cycles using a flip-flop circuit for shifting and outputting an input signal in synchronization with a clock signal.
Japanese Patent Application Laid-open No. 07-122065A (hereinafter called Patent Document 2) in turn describes a memory control circuit for reducing power consumption by shifting a refresh timing from one memory bank to another, in a manner similar to the aforementioned Patent Document 1. The memory control circuit described in Patent Document 2 comprises a control register, a counter, and a bank separation circuit for performing logic operations, and the refresh timing is shifted from one memory bank to another in units of fixed cycles of a signal output from the counter. Further, Patent Document 2 describes a control method for refreshing every two banks, for example, while shifting the refresh timing.
Japanese Patent Application Laid-open No. 2003-91989A (hereinafter called Patent Document 3) describes a semiconductor memory device which solely refreshes part of an array selected in accordance with an external instruction when it performs a self-refresh. In the semiconductor memory described in Patent Document 3, as an external instruction is input, a range of address bits to be accessed is manipulated by an internal address generator circuit for generating a refresh address. In the semiconductor memory device described in Patent Document 3, power consumption is reduced by enabling part of the array to be selected, thereby extending the cycle of a distributed refresh operation.
In recent years, a lower supply voltage and a higher speed have been progressively achieved in a variety of semiconductor devices, and noise voltages of a power supply system generated in association with abrupt changes in current have increasingly hindered stable operations of devices. For example, in DDR-SDRAM (Double Data Rate-Synchronous Dynamic Random Access Memory), larger importance has been placed on techniques for reducing noise voltages of a power supply system as newer versions have advanced from DDR to DDR2 and to DDR3.
A power supply system for DRAM can be classified into a core block (VDD) and an I/O block (VDDQ). In these blocks, a refresh operation which involves large current consumption constitutes a principal noise factor in the core block. The refresh operation refers to recharging capacitors for storing data, and DRAM must perform a refresh operation for every predetermined period without fail in order to hold stored data.
The refresh operation is executed, for example, in response to an auto-refresh command (REF command) input from the outside. Alternatively, the refresh operation is executed by generating a REF command at certain time intervals within a DRAM (so-called self-refresh operation). Generally, as a REF command is issued, particular word lines are simultaneously activated within all memory banks of a DRAM. Also, as the REF command is issued, an ACT command (activation of word lines) and a PRE command (deactivation of word lines and precharge of bit lines) are generated within the DRAM, and the ACT command and PRE command are output to all the memory banks. In this event, an address for specifying a particular word line (word line address) is automatically generated by a refresh counter circuit or the like contained in the DRAM.
When particular word lines are simultaneously activated in all the memory banks in this way, a large current instantaneously flows from the power supply system to each memory bank, causing a large noise voltage to occur in the power supply system.
FIGS. 1A and 1B are diagrams showing an exemplary refresh operation in a semiconductor device of a related art. FIG. 2A in turn is a chart showing an exemplary waveform of current from a power supply during a refresh operation shown in FIGS. 1A and 1B, and FIG. 2B is a chart showing an exemplary waveform of voltage from the power supply during the refresh operation shown in FIGS. 1A and 1B.
In the following, a description will be given of why a large noise voltage occurs in the power supply system of the related art semiconductor device, giving, as an example, a semiconductor device (DRAM) which comprises eight memory banks.
First, in a refresh operation shown in FIG. 1B (hereinafter called “Case B”), an ACT command is simultaneously issued to all memory banks (Bank0-Bank7), and after the lapse of a certain time, a PRE command is simultaneously issued to all the memory banks. In this event, as shown in [Case B] of FIG. 2A, a large current flows from the power supply system when the ACT command is issued and when the PRE command is issued. Also, as shown in [Case B] in FIG. 2B, a supply voltage largely fluctuates due to the large current flowing from the power supply system. The fluctuations in the supply voltage appear as a noise voltage which adversely affects the operation of the device.
In the aforementioned Patent Documents 1 and 2, the ACT command is issued at a time point shifted by tRF_min from one memory bank to another, and the PRE command is issued at a time point shifted by tRF_min from one memory bank to another, as shown in FIG. 1A (hereinafter called “Case A”), in order to reduce such noise voltages. Here, period tRFC_min shown in FIG. 1A is a period which must be minimally ensured from the time the ACT command is issued to the first memory bank to the time when the refresh operation ends in the last memory bank, and is generally defined as a specified value. Period tRC in turn is a period which must be minimally ensured from the time the ACT command is issued to a memory bank to the time when the PRE command is issued to the same memory bank, and is generally defined as a specified value as well.
Accordingly, in order to satisfy the foregoing specified values, respectively, tRF_min must be set within a value calculated by the following Equation (1):tRF_min=(tRFC_min−tRC)/(Number of Banks−1)  (1)
With the employment of the refresh operation shown in FIG. 1A, the current which flows from the power supply system in association with the refresh operation is averaged, as shown in [Case A] of FIG. 2A, so that a peak current is largely reduced as compared with [Case B]. Thus, the supply voltage fluctuates less as compared with [Case B], as shown in [Case A] of FIG. 2B, leading to a reduction in noise voltage.
In this regard, since the time required for a refresh operation is generally on the order of 100 ns, it is thought that the power supply system suffers a noise voltage which has a fundamental wave at a frequency in a 10-MHz band during the refresh operation.
Generally, the impedance of a power supply system is mainly comprised of inductance (L) in a band of several tens of MHz (i.e., the higher the frequency, the larger the impedance), and harmonic components of a current flowing from the power supply system (supply current) largely affect the amount of noise voltage as well.
In the techniques described in the aforementioned Patent Documents 1 and 2, since the waveform of the supply current is substantially trapezoidal, as shown in [Case A] of FIG. 2A, the supply current contains large harmonic components. For this reason, when the production of newer semiconductor devices further advances, stable operations of devices are likely to be largely hindered by power supply noise caused by the harmonic components.